2003

H.-J. Schlebusch, G. Smith, D. Sciuto, D. Gajski, C. Mielenz, C.K. Lennard, F. Ghenassia, S. Swan, J. Kunkel, Transaction based design: another buzzword or the solution to a design problem? Proc. DATE 2003, Design, Automation and Test in Europe Conference, 2003,  Munich, March 3-7, pp.876-877.

C. Brandolese, L: Ceresoli, W. Fornaciari, D. Sciuto, Library functions timing characterization for source-level analysis, Proc. DATE 2003, Design, Automation and Test in Europe Conference, 2003, Munich March 3-7, 2003.

L. Salvemini, M. Sami, D. Sciuto, C. Silvano, V. Zaccaria, R. Zafalon, A Methodology for the Efficient Architectural Exploration of Energy-Delay Trade-offs for Embedded Systems, Proc. SAC03, The 2003 ACM SIGAPP Symposium on Applied Computing, 9-12 March 2003, Melbourne, Florida, USA, pp.672-678.

G. Agosta, F. Bruschi, D. Sciuto,  Static Analysis of Transaction Level Models, Proc. Design Automation Conference DAC 2003, Anaheim, CA, USA, June 2003, pp. 448-453.

F. Salice, W. Fornaciari, L. Pomante, D. Sciuto. An Internal Representation Model for System-Level Co-Design of Heterogeneous Multiprocessor Embedded System, Forum on Specification and Design Languages (FDL 2003), Francoforte (Germania), Settembre 2003, pp. 669-679

C. Bolchini, F. Salice, D. Sciuto, R. Zagaglia, An Integrated Approach for Designing Self-Checking FPGAs, Proc. IEEE Defect and Fault Tolerance in VLSI Systems, DFT 2003, Cambridge, MA, USA, pp. 443-450, 2003.

Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, Mining Interesting Patterns from Hardware-Software Codesign Data with the Learning Classifier System XCS, IEEE Proceedings of the 2003 Congress on Evolutionary Computation (CEC 2003), pp. 1486—1492, 2003, 9-12 December, Canberra, Australia.

2004

G. Agosta, F. Bruschi, D. Sciuto, Synthesis of dynamic class loading specifications on reconfigurable hardware, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004. DELTA 2004, 28-30 Jan. 2004, pp. 431 - 433

F. Ferrandi, P. Lanzi, D. Sciuto, M. Tanelli, System-level metrics for hardware/software architectural mapping, Second IEEE International Workshop on Electronic Design, Test and Applications, 2004. DELTA 2004, 28-30 Jan. 2004, pp. 231 - 236

C. Brandolese, W. Fornaciari, F. Salice, D. Sciuto, Analysis and Modeling of Energy Reducing Source Code Transformations, IEEE/ACM Design Automation and Test in Europe (DATE'04), Paris, France,  February 16-20, pp. 306 - 311 Vol.3, 2004.

G. Beltrame, G. Palermo, D. Sciuto), C. Silvano, Plug-in of Power Models in the StepNP  Exploration Platform: Analysis of Power/Performance Trade-offs, IEEE CASES 2004 - International ACM Conference on Compilers, Architectures and  Synthesis for Embedded Systems, Washington DC, USA, 22-25 September, 2004,  pp. 85-92.

C. Bolchini, A. Miele, F. Salice, D. Sciuto, L. Pomante, Reliable system co-design: the FIR case study, 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2004. DFT 2004, 10-13 Oct. 2004 pp. 433 – 441

2005

C. Bolchini, F. Salice, D. Sciuto, L. Pomante, Reliable system specification for self-checking data-paths, IEEE/ACM Proceedings Design, Automation and Test in Europe, 2005, pp.1278 - 1283 Vol. 2

F. Ferrandi, M. Santambrogio, D. Sciuto, A Design Methodology for Dynamic Reconfiguration: The Caronte Architecture, 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Reconfigurable Architecture Workshop – RAW,  vol. 04, no. 4, Aprile  2005

A. Donato, F. Ferrandi, M. Redaelli, M. Santambrogio, D. Sciuto, Caronte: a complete methodology to implement partially dynamically self-reconfiguring embedded systems on modern FPGA, 2005 IEEE Symposium on Field-Programmable Custom Computing Machines – FCCM05, p. 321 - 322, FCCM, Aprile 2005

G. Agosta, F. Bruschi, M. Santambrogio, D. Sciuto, A Data Oriented Approach to the Design of Reconfigurable Stream Decoders, proc. di IEEE 2005 3rd Workshop on Embedded Systems for Real-Time Multimedia, New York, Settembre 2005, pp. 107-112.

G. Agosta, F. Bruschi, D. Sciuto, Aspect Orientation in System Level Design, Proc. Forum on Specification & Design Languages", Lausanne, Settembre 2005

F. Bruschi, F. Moro, D. Sciuto, Mapping Interface Method Calls over OCP Buses, Proc. Forum on Specification & Design Languages", Lausanne, Settembre 2005

A. Donato, F. Ferrandi, M. Redaelli, M. Santambrogio, D. Sciuto, Operating system support for dynamically reconfigurable SoC architectures, IEEE International SOC Conference – IEEE-SOCC 2005, proc. P. 235 – 238, September 2005

P. Faverio, D. Sciuto, A. Ravarini, Critical Success Factors in SME ERP Project Management: Preliminary Results, Proceedings “eChallenges e-2005”, Lubiana (SLO),19-21 Ottobre, 2005

A. Donato, F. Ferrandi, M. Redaelli, M. Santambrogio, D. Sciuto, Exploiting partial dynamic reconfiguration for SoC design of complex application on FPGA platforms, Proc. IFIP VLSI-SOC 2005, p. 179 – 184, October 2005

F. Ferrandi, M. Redaelli, M. Santambrogio, D. Sciuto, Solving the Coloring Problem to Schedule on Partially Dynamically Reconfigurable Hardware, Proc. IFIP VLSI-SOC 2005, p. 97 – 102, October 2005

C. Bolchini, A. Miele, F. Salice, D. Sciuto, A model of soft error effects in generic IP processors, Proc. 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2005. DFT 2005, 03-05 October 2005 pp.334 - 342

2006

R. Cordone, F. Ferrandi, M. Santambrogio, G. Palermo, D. Sciuto, Using speculative computation and parallelizing techniques to improve scheduling of control based designs, Proc. IEEE/ACM Asia and South Pacific Conference on Design Automation, 2006, January 2006, pag. 898-904.

G. Beltrame, D. Sciuto, C. Silvano, D. Lyonnard, C. Pilkington, Exploiting TLM and Object Introspection for System-Level Simulation, IEEE/ACM Proc. Design, Automation and Test in Europe, 2006. DATE '06, Volume 1,  6-10 March 2006 pp.100-105

Simone Borgio, Davide Bosisio, Matteo Monchiero, Antonino Tumeo, Fabrizio Ferrandi, Marco Santambrogio, and Donatella Sciuto. “Hardware DWT accelerator for MultiProcessor System On-Chip on FPGA.” In Proceedings of IEEE IC-SAMOS’06 – Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece. July 17–20, 2006 , pp.

C. Amicucci, F. Ferrandi, M. D. Santambrogio, D. Sciuto. “SyCERS: a SystemC design exploration framework for SoC reconfigurable architecture”, ERSA'06: The 2006 International Conference on Engineering of Reconfigurable Systems & Algorithm, pag.: 63-69, June 2006

G. Agosta, F. Bruschi, M. D. Santambrogio, D. Sciuto.“Synthesis of Object Oriented Models on Reconfigurable Hardware”, ERSA'06: The 2006 International Conference on Engineering of Reconfigurable Systems & Algorithm, pag.: 249-250, June 2006

F. Ferrandi, A. Mele, V. Rana, M. D. Santambrogio, D. Sciuto. “A Caronte-oriented approach to a network-based educational infrastructure.”, 6th European Workshop on Microelectronics Education - EWME 06, pag.: 133-136, June 2006

M. D. Santambrogio, D. Sciuto. “Partial dynamic reconfiguration: the Caronte approach. A new degree of freedom in the HW/SW codesign.”, FPL 06: 16th International Conference on Field Programmable Logic and Applications, pag.: 945-946, August 2006

Tiziana Gravagnoli, Fabrizio Ferrandi, Pier Luca Lanzi, Donatella Sciuto, “Automatic Test Pattern Generation with BOA”, Proceedings of Parallel Problem Solving from Nature - PPSN IX, 9th International Conference, Reykjavik, Iceland, September 9-13, 2006, pp. 423-432

M. Giorgetta, M. D. Santambrogio, D. Sciuto, P. Spoletini. “A graph-coloring approach to the allocation and tasks scheduling for reconfigurable architectures.” 14th IFIP International Conference on Very Large Scale Integration - IFIP VLSI-SOC 2006, pag.: 24-29, October 2006

M. Murgida, A. Panella, V. Rana, M. D. Santambrogio, D. Sciuto. “Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow”, 14th IFIP International Conference on Very Large Scale Integration - IFIP VLSI-SOC 2006, pag.: 74-79, October 2006

G. Beltrame, E. Bensoudane, P. Paulin, D. Sciuto, C. Silvano, “An Application Mapping Methodology and Case Study for Multi-Processor On-Chip Architectures, 14th IFIP International Conference on Very Large Scale Integration - IFIP VLSI-SOC 2006, pag. 146-151, October 2006

G. Beltrame, D. Bruschi, D. Sciuto, C. Silvano, “Decision-Theoretic Exploration of Multi-Processor Platforms”, Proc. ACM/IEEE CODES+ISSSS06, Seoul, Korea, October 2006, pp.205-210.

C. Bolchini A. Miele M. Rebaudengo D. Sciuto L. Sterpone M. Violante, Combined software and hardware techniques for the design of reliable IP processors, Proc. IEEE Defect and Fault Tolerance in VLSI Systems Symposium, DFTS 2006 Arlington, VA, USA pp. 265 – 273, 2006.

F. Ferrandi, M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto. “Dynamic Reconfiguration: Core Relocation via Partial Bitstreams Filtering with Minimal Overhead”, International Symposium on System-on-Chip - SoC 06, pag.: 33-36, November 2006

V. Rana, S. Ogrenci Memik, M. D. Santambrogio, D. Sciuto “Combining Hardware Reconfiguration and Adaptive Computation for a Novel SoC Design Methodology”, International Conference on Field Programmable Technology - FPT 06, pag.: 293-296, December 2006

2007

V. Rana, M. Santambrogio, D. Sciuto, B. Kettelhoit, M. Koester, M. Porrmann, U. Ruckert,  Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux, IEEE International Parallel and Distributed Processing Symposium, 2007. IPDPS 2007, 26-30 March 2007 Page(s):1 - 8

A. Tumeo, M. Monchiero, G. Palermo, F: Ferrandi, D. Sciuto, An Internal Partial Dynamic Reconfiguration Implementation of the JPEG Encoder for Low-Cost FPGAs, IEEE Computer Society Annual Symposium on VLSI, 2007. ISVLSI '07, 9-11 March 2007 Page(s):449 - 450

S. Corbetta, F. Ferrandi.; M. Morandi, M. Novati, M.D. Santambrogio, D. Sciuto, Two Novel Approaches to Online Partial Bitstream Relocation in a Dynamically Reconfigurable System, IEEE Computer Society Annual Symposium on VLSI, 2007. ISVLSI '07, 9-11 March 2007 Page(s):457 - 458

A.P.E. Rosiello, F.  Ferrandi, D. Pandini, D. Sciuto, A Hash-based Approach for Functional Regularity Extraction During Logic Synthesis, IEEE Computer Society Annual Symposium on VLSI, 2007. ISVLSI '07, 9-11 March 2007 Page(s):92 - 97

Tumeo, A.; Monchiero, M.; Palermo, G.; Ferrandi, F.; Sciuto, D.; A Pipelined Fast 2D-DCT Accelerator for FPGA-based SoCs, IEEE Computer Society Annual Symposium on VLSI, 2007. ISVLSI '07, 9-11 March 2007 Page(s):331 - 336

F. Ferrandi, L. Fossati, M. Lattuada, G. Palermo, D. Sciuto, A. Tumeo, “Partitioning and Mapping for the hArtes European Project”, Workshop on Directions in FPGAs and Reconfigurable Systems: Design, Programming and Technologies for adaptive heterogeneous Systems-on-Chip and their European Dimensions, held during Design Automation and Test in Europe 2007 (DATE '07),

20 April 2007 Nice, France. pp. 47-52. (Invited Paper).

V. Rana, M. Santambrogio,  D. Sciuto, “Dynamic Reconfigurability in Embedded System Design”,

IEEE International Symposium on Circuits and Systems, 2007. ISCAS 2007, 27-30 May 2007 Page(s):2734 - 2737

F. Ferrandi, L. Fossati, M. Lattuada, G. Palermo, D. Sciuto, A. Tumeo, “Automatic Parallelization of Sequential Specifications for Symmetric MPSoCs”, International Embedded Systems Symposium 2007 (IESS ’07), pages 179–192, 2007

G. Agosta, F. Bruschi, G. Pelosi, D. Sciuto, “A Unified Approach to Canonical Form-based Boolean Matching”, Design Automation Conference, 2007. DAC '07. 44th ACM/IEEE, 4-8 June 2007 Page(s):841 - 846

A. Tumeo, M. Branca, L. Camerini, M. Monchiero, G. Palermo, F. Ferrandi, D. Sciuto, An Interrupt Controller for FPGA-based Multiprocessors, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2007. IC-SAMOS 2007. 16-19 July 2007 Page(s):82 - 87

F. Ferrandi, P.L. Lanzi, G. Palermo, C. Pilato, D. Sciuto, A. Tumeo,  An Evolutionary Approach to Area-Time Optimization of FPGA designs, International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, 2007. IC-SAMOS 2007. 16-19 July 2007,  Page(s):145 - 152

A. Tumeo, M. Monchiero, G. Palermo, Ferrandi F., D. Sciuto, “Self Reconfigurable Implementation of the JPEG Encoder”, Proc. IEEE International Conference on Application-specific Systems, Architectures and Processors, Montréal (Québec), Canada, July 9-11, 2007 –pp. 24-29.

C. Pilato, G. Palermo, A. Tumeo, Ferrandi F., P. L. Lanzi, D. Sciuto, “Fitness Inheritance in Evolutionary and Multi-Objective High-Level Synthesis”, Proc. IEEE CEC 2007 - Congress on Evolutionary Computation, Singapore, Sept. 25-28 2007, pp. 3459-3466.

G. Beltrame, C. Bolchini, L. Fossati, A. Miele, D. Sciuto, “A Framework for Reliability Assessment and Enhancement in Multi-Processor Systems- On-Chip”, IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, DFT 2007, September 2007, pp.132-140.

V. Rana, C. Sandionigi, M. D. Santambrogio, D. Sciuto, “An adaptive genetic algorithm for dynamically reconfigurable modules allocation”, 15th IFIP VLSI-SOC 2007, 15th International Conference on Very Large Scale Integration, pp. 128-133, October 2007.

M. D. Santambrogio, V. Rana, S. Ogrenci Memik, D. Sciuto “A Novel SoC Design Methodology Combining Adaptive Software and Reconfigurable Hardware”, 25th International Conference on Computer-Aided Design, ICCAD 2007,  pp. 303 - 308,  2007.

2008

G. Beltrame, C. Bolchini, L. Fossati, A. Miele, D. Sciuto, “ReSP: A Non-Intrusive Transaction-Level Reflective MPSoC Simulation Platform for Design Space Exploration”, IEEE Asia and South Pacific Design Automation Conference, ASP-DAC 2008, pp.673-678

C. Curino, V. Rana, F. Redaelli, M. D. Santambrogio, D. Sciuto, “The Shining embedded system design methodology based on self dynamic reconfigurable architectures,” 13th ASP-DAC 2008, 13th Asia and South Pacific Design Automation Conference, pp. 595-600.

A. Montone, M. D. Santambrogio, D. Sciuto, “A Design Workflow for the Identification of Area Constraints in Dynamic Reconfigurable Systems”, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 08, proc. p. 450 - 453, Hong Kong, January 23 - 25, 2008

A. Cuoccio, P. R. Grassi, V. Rana, M. D. Santambrogio, D. Sciuto, “A Generation Flow for Self-Reconfiguration Controllers Customization”,4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 08, proc. p. 279 - 284, Hong Kong, January 23 - 25, 2008

A. Meroni, V. Rana, M. D. Santambrogio, D. Sciuto, “A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow”, 4th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 08, proc. p. 405 - 409, Hong Kong, January 23 - 25, 2008.

F. Redaelli, M. D. Santambrogio, D. Sciuto, “Task scheduling with configuration prefetching and anti-fragmentation techniques on dynamically reconfigurable systems”, Design, Automation and Test in Europe, DATE 08, proc. p. 519 - 522, Munich, Germany, March 10 - 14, 2008

A. Tumeo, M. Branca, L. Camerini, M. Ceriani, M. Monchiero, G. Palermo, F. Ferrandi, D. Sciuto.

“A dual-priority real-time multiprocessor system on FPGA for automotive applications”, Proc. IEEE DATE 2008 – Design, Automation and Test in Europe, Munich (Germany). March 10-14 2008. pp. 1039-1045.

Christian Pilato, Daniele Loiacono, Fabrizio Ferrandi, Pier Luca Lanzi, and Donatella Sciuto. “A multi-objective genetic algorithm for design space exploration in high-level synthesis”, Proc. ISVLSI 2008 - IEEE Computer Society Annual Symposium on VLSI, Montpellier, France, April 7-9 2008. pp. 417-422

M. Morandi, M. Novati, M. D. Santambrogio, D. Sciuto, “Core allocation and relocation management for a self dynamically reconfigurable architecture”, IEEE Computer Society Annual Symposium on VLSI, ISVLSI 08, proc. p. 286 - 291, Montpellier, France, April 7 - 9, 2008

M. D. Santambrogio, D. Sciuto, “Design methodology for partial dynamic reconfiguration: a new degree of freedom in the HW/SW codesign”, 22th IEEE International Parallel and Distributed Processing Symposium (IPDPS'08) - Reconfigurable Architecture Workshop - RAW, IEEE online proceedings, Miami, Florida, USA, April 14 - 18, 2008, Keynote speech

A. Montone, V. Rana, M. D. SANTAMBROGIO, D. Sciuto. HARPE: a Harvard-based Processing Element Tailored for Partial Dynamic Recongurable Architectures,  In: IEEE International Parallel and Distributed Processing Symposium (IPDPS'08) - Reconfigurable Architecture Workshop - RAW 2008, pp. 1- 8, 14-18 April 2008, Miami, Fl, USA.

F. Cancare', M.D. Santambrogio, D. Sciuto. A Design Flow Tailored for Self Dynamic Reconfigurable Architecture,  In: Parallel and Distributed Processing, 2008. IPDPS 2008. IEEE International Symposium on . 14/4/2008 -18/4/2008, Miami, FL, pp.1-8 (online proceedings)

C. Pilato, D. Loiacono, F. Ferrandi, P. L. Lanzi, D. Sciuto, “High-level Synthesis with Multi-objective Genetic Algorithm: a Comparative Encoding Analysis”, Proc. IEEE CEC 2008 –  Congress on Evolutionary Computation, Hong Kong (China), June 1-6, 2008, pp.

A. Tumeo , M. Monchiero, G. Palermo, F. Ferrandi and D. Sciuto. "Lightweight DMA Management Mechanisms for Multiprocessors on FPGA.", Proc. IEEE ASAP'08 - 19th International Conference on Application-specific Systems, Architectures and Processors, Leuven, Belgium July 2-4 2008, pp. 281-286.

Antonino Tumeo, Christian Pilato, Fabrizio Ferrandi, Donatella Sciuto, Pier Luca Lanzi,  “Ant Colony Optimization for Mapping and Scheduling in Heterogeneous Multiprocessor Systems”,

Proc. IEEE Int. Conf. SAMOS VII: Embedded Computer Systems: Architectures, MOdeling, and Simulation, Samos, Greece, July 21-24 2008, pp. 142-149.

S. Corbetta, V. Rana, M. D. Santambrogio, D. Sciuto, “A Light-Weight Network-on-Chip Architecture for Dynamically Reconfigurable Systems”, Proceedings of IEEE IC-SAMOS'08 - Embedded Computer Systems: Architectures, MOdeling, and Simulation, proc. p. 49 - 56, Samos, Greece, July 21 - 24, 2008

C. Bolchini; A. Miele; D. Sciuto. Fault Models and Injection Strategies in SystemC Specifications,  EUROMICRO Conf. on Digital System Design - Architectures, Methods and Tools, pp. 88- 95, Sepetmebr 2008, Parma, ITALY.

M. D. Santambrogio, V. Rana, D. Sciuto, “Operating System Support for Online Partial Dynamic Reconfiguration Management”,18th International Conference on Field Programmable Logic and Applications, FPL 08, proc. p. 455 - 458, Heidelberg, Germany, September 8 - 10, 2008

Giovanni Beltrame, Luca Fossati, and Donatella Sciuto. High-Level Modeling and Exploration of Reconfigurable MPSoCs. In Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems, pages 330–337. IEEE Computer Society, 2008

Giovanni Beltrame, Luca Fossati, and Donatella Sciuto. Concurrency Emulation and Analysis of Parallel Applications for Multi-Processor System-on-Chip Co-Design. In Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis, pages 7–12, Atlanta, GA, USA, 2008

Francesco Bruschi, Vincenzo Rana, Donatella Sciuto  An Architecture for Dynamically Reconfigurable Real Time Audio Processing Systems, . In: IEEE Workshop on Embedded Systems for Real-time Multimedia ESTIMedia 2008. October 2008, Atlanta, Georgia, USA, pp. 81- 86

V. Rana, D. A. Atienza, M. D. Santambrogio, D. Sciuto, G. De Micheli, “A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication”,International Conference on Very Large Scale Integration, IFIP VLSI-SoC 2008, proc. p.321 - 326, Rhodes Island, Greece, October 13 - 15, 2008. Selected among the conference best papers and invited for a publication in the book: VLSI-SoC, Springer

2009

F. Cancare, M. D. Santambrogio, D. Sciuto, “An Application-centered Design Flow for Self Reconfigurable Systems Implementation”,14th Asia and South Pacific Design Automation Conference, ASP-DAC 2009, proc. p. 248- 253, Yokohama, Japan, January 19 - 22, 2009

A. Tumeo, M. Branca, L. Camerini, M. Ceriani, M. Monchiero, G. Palermo, F. Ferrandi, D. Sciuto, “Prototyping pipelined applications on a heterogeneous fpga multiprocessor virtual platform”. In Proceedings of IEEE/ACM Asia and South Pacific Design Automation Conference (ASPDAC '09), Yokohama, Japan, January 2009, pages 317–322

A. Tumeo, C. Pilato, G. Palermo, F. Ferrandi, D. Sciuto, “HW/SW methodologies for synchronization in FPGA multiprocessors”, in Proceeding of the ACM/SIGDA international symposium on Field programmable gate arrays (FPGA 2009), Monterey, CA, USA, February 22-24, 2009, pp. 265-268.

Giovanni Beltrame, Luca Fossati, and Donatella Sciuto. A Real-Time application design methodology for MPSoCs. In Design Automation and Test in Europe (DATE), pages 767–772, 2009

M. Branca, L. Camerini, F. Ferrandi, P. L. Lanzi, C. Pilato, D. Sciuto, A. Tumeo, “Evolutionary algorithms for the mapping of pipelined applications onto heterogeneous embedded systems”, in Proceedings of the 11th Genetic And Evolutionary Computation Conference (GECCO 2009), Montreal, Canada, July 8-12, 2009, pp. 1435-1442.

A. Tumeo, S. Borgio, D. Bosisio, M. Monchiero, G. Palermo, F. Ferrandi, D. Sciuto. “A multiprocessor self-reconfigurable jpeg2000 encoder”. In Proceeding of 16th Reconfigurable Architectures Workshop (RAW 2009), Rome, Italy, May 23-29, 2009, pp.  1-8.

M. D. Santambrogio, M. Morandi, M. Novati, D. Sciuto, “A Runtime Relocation Based Work Flow for Self Dynamic Reconfigurable Systems Design”, 19th International Conference on Field Programmable Logic and Applications, FPL 09, pp. 86 - 91, Prague, Czech Republic, August 31 - September 2, 2009.

V. Rana, S. Murali, D. Atienza, M. D. Santambrogio, L. Benini and D. Sciuto, “Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems”, International Conference on Hardware-Software Codesign and System Synthesis, CODES+ISSS 09,  Grenoble, France, October 11 - 16, 2009

2010

F. Ferrandi, C. Pilato, D. Sciuto, A. Tumeo, “Mapping and scheduling of parallel C applications with Ant Colony Optimization onto heterogeneous reconfigurable MPSoCs”, 2010 15th Asia and South Pacific  Design Automation Conference (ASP-DAC), pp.799 – 804, January 2010

A. Tumeo, F. Regazzoni, G. Palermo, F. Ferrandi, D. Sciuto,  “A reconfigurable multiprocessor architecture for a reliable face recognition implementation”, IEEE/ACM Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010,  pp. 319 – 322, March 2010.

A. Montone, M.D. Santambrogio, D. Sciuto, “Wirelength driven floorplacement for FPGA-based partial reconfigurable systems” 2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), pp. 1 – 8, May 2010

M. D. Santambrogio, P.R.  Grassi, D. Candiloro, D. Sciuto,  “Analysis and validation of partially dynamically reconfigurable architecture based on Xilinx FPGAs”  2010 IEEE International Symposium on Parallel & Distributed Processing, Workshops and Phd Forum (IPDPSW), pp. 1 – 4, May 2010

M D.  Santambrogio, V. Rana, D. Sciuto, S. Corbetta,  “Multiple communication-domains design in FPGA-based Systems-on-Chip”, IEEE 2010 5th International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS), pp. 1-6, 2010.